Electro Static Discharge (ESD) is a momentary flow of static charges that occurs between two surfaces with different potentials when the two surfaces come in contact. ESD is a major consideration in design and manufacture of semiconductor Integrated Circuits (ICs) because of the impact ESD has on production yields and product quality. ESD can occur in any one of the following conditions: when a charged human body touches an IC, when a charged IC touches a grounded surface, when a charged machine touches an IC, or when an electrostatic field induces a voltage across a dielectric sufficient to break it down. ESD can have serious detrimental effects on all semiconductor ICs and the electronic devices that contains them.
ESD problems are increasing in the electronics industry because of the trends toward higher speed and smaller device sizes. As the size of electronic devices become smaller by the day, unintentional contact between two components of different potential within the electronic device presents a challenge for designing and manufacturing the electronic devices. Further, ESD is a significant cause of rejection during the manufacturing of electronic devices and is important to the functioning of any electronic device throughout its lifetime. The input and output pins on an electronic device are especially vulnerable to ESD since users attach or detach external devices, such as antennas, on these pins.
Metal oxide semiconductors (MOS) are known to be especially susceptible to ESD, primarily because ESD can destroy and irreparably damage the thin oxide layer of the MOS device. Bipolar junction transistors (BJT) are usually considered to be less susceptible to ESD than MOS, but small heterojunction bipolar transistors (HBT), such as InGaP HBTs, are particularly susceptible to damage from ESD. Other structures that are susceptible to ESD include integrated capacitors and adjacent metal lines on a semiconductor die.
ESD can damage or reduce the life of an electrical device by exceeding the breakdown levels of dielectrics used in integrated circuits. Dielectrics susceptible to ESD often include capacitors and passivation dielectrics. ESD may also damage the semiconductor layers in an active device.
A common approach to reduce the damage caused by an unwanted ESD pulse is to provide a shunt path that directs the ESD pulse current away from the electrical device. Another approach to reduce the damage caused by the ESD pulse is by providing a robust path around, or parallel to, a sensitive device by adding a protection circuit.
In Radio Frequency (RF) communication circuits/components, the ESD pulse is reduced by employing a specially designed ESD protection circuit connected to the RF output port of an RF power amplifier. Conventionally, a separate circuit comprising a clamp transistor is implemented in RF amplifiers to protect them from ESD damages. Much progress has been made in the last few years with regard to technologies that reduce the effect of an ESD pulse on RF applications; this has led to the introduction of various new ESD circuits.
US patent publication 2004/0057172 A1 discloses ESD protection circuits that provide current shunt paths to protect electrical devices. FIG. 1 is a schematic diagram illustrating an ESD protection circuit 100 disclosed in the US patent publication 2004/0057172. The circuit shown in FIG. 1 includes a first port 102, a second port 104, and two branches 106 and 108. The two branches 106 and 108 are connected in parallel to each other between the first port 102 and the second port 104.
As shown in FIG. 1, the branch 106, the forward branch, provides a path for excess current from the first port 102 to the second port 104. The branch 108, the reverse branch, provides a path for excess current from the second port 104 to the first port 102.
The branch 106 shown in FIG. 1, comprises a base diode stack 110, a resistor 112, a triggering transistor 114, and a collector diode stack 116. The base diode stack 110 is connected in series with the resistor 112 in a voltage divider configuration. A base terminal of the triggering transistor 114 is connected to the voltage divider. An emitter terminal of the triggering transistor 114 is connected to the second port 104. The collector diode stack 116 is connected between the first port 102 and a collector terminal of the triggering transistor 114 and dissipates the bulk of the excess power through the branch 106 of the circuit.
Further, the base diode stack 110 is selected to set the triggering threshold of the branch 106. The resistor 112 is selected to keep the triggering transistor 114 switched off during normal operation and adjust the switch-off time of the triggering transistor 114 during an ESD pulse. The collector diode stack 116 may include one or more diodes connected in series or one or more transistors configured as diodes, connected in series.
The branch 108 shown in FIG. 1 comprises a reverse triggering transistor 118, a reverse collector diode stack 120, and a reverse base diode stack 122. In general, the reverse triggering transistor 118 remains switched off until the voltage at the second port 104 exceeds the sum of the diode junction drops in the reverse base diode stack 122 and the base-emitter turn-on voltage (the base-emitter diode junction drop) of the reverse triggering transistor 118.
In the circuit shown in FIG. 1, the triggering transistor 114 is generally switched off in order to prevent current flow from the high voltage node (i.e. the first port 102) to the low voltage node (i.e. the second port 104). When the voltage rises above the sum of the diode junction drops in the base diode stack 110 and the base-emitter turn-on voltage (the base-emitter diode junction drop) of the reverse triggering transistor 118, the current from the high voltage node 102 flows through the base diode stack 110 and through the resistor 112. As the current increases further, the voltage across the resistor 112 turns on the triggering transistor 114 on and allows the current to flow through the collector diode stack 116.
Further, when the reverse base diode stack 122 begins conducting current, the reverse triggering transistor 118 switches on after the transistor's base-emitter voltage drop is exceeded and a current begins to flow through the reverse collector diode stack 120 from the second port 104 to the first port 102.
In view of the above described illustration of FIG. 1, US patent publication 2004/0057172 provides a solution to protect electronic devices from ESD pulse. Protection is achieved by connecting an ESD protection circuit with the ports of the electronic device where protection from ESD pulse is required. Though the circuit provides protection from ESD pulse, it is too complex and bulky to be implemented in many RF applications. Therefore, in order to overcome the disadvantages and shortcomings of this circuit, an advanced ESD protection circuit is disclosed in U.S. Pat. No. 7,586,720.
U.S. Pat. No. 7,586,720, a patent by the inventor of the present invention, discloses an improved compact ESD protection circuit that uses a reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD pulse current to ground. The circuit disclosed in this patent will be described in detail later in the specification.
Although the circuit disclosed in US patent publication 2004/0057172 is effective in preventing damage from ESD pulse events, the diode capacitances detrimentally effect the operation at RF frequencies. Furthermore, the large part-count of the circuit increases the die area required to incorporate the circuit into an RF design. The compact ESD protection circuit disclosed in U.S. Pat. No. 7,586,720 replaces the large and complex components of the circuit disclosed in US patent publication 2004/0057172 with three small transistors resulting in the requirement of a very small die area as compared to the circuit disclosed in US patent publication 2004/0057172. The ESD circuit disclosed in U.S. Pat. No. 7,586,720 exhibits advantages over the circuit disclosed in US patent publication 2004/0057172, as it can be used to protect RFin pins in power amplifiers as well as DC pins. Further, the die area of the circuit in U.S. Pat. No. 7,586,720 is smaller than the die area of the circuit in US patent publication 2004/0057172. However, the die area of the circuit in U.S. Pat. No. 7,586,720 is still too large and costly for compact and/or very low cost devices. Therefore there is a need for an effective low cost ESD protection device that utilizes a smaller die area and is capable of operating at high frequencies.